1. Field of the Invention
The present invention relates to a method of forming a thin film interconnect disposed on a substrate of liquid-crystal display or the like, and also relates to a thin film interconnect formed by the same method.
Priority is claimed on Japanese Patent Application No. 2012-032058 filed on Feb. 16, 2012, the content of which is incorporated herein by references.
2. Description of Related Art
Liquid crystal displays, plasma displays, organic liquid crystal displays, inorganic liquid crystal displays or the like are known as flat panel displays that are operated by active matrix method utilizing thin film transistors (hereafter referred to as TFTs).
In flat panel displays (hereafter referred to as FPDs) using these TFTs, interconnects formed of metal film adhere to a surface of a substrate such as a glass substrate, and each TFT is formed on the cross section of grid-like interconnects made of the metal film.
FIG. 1 is a vertical cross section schematically showing a structure of a generally known TFT. This TFT is constituted of sequentially stacked films that include a gate electrode film 2 made of a pure copper film, a silicon nitride film 3, a Si semiconductor film 4, a silicon oxide barrier film 5 stacked sequentially on the glass substrate 11, and a drain electrode film 7 and a source electrode film 8 that are stacked on the barrier film 5 and that are separated by a trench 6.
During production of TFTs having such a stacked structure, the trenches that separate drain electrode films and source electrode films are formed by wet etching and plasma etching.
At that time, the surface of Si semiconductor film exposed to the bottom surface of the trench has an extremely unstable state. That is, uncombined bonds (dangling bonds) increase in the bottom surface of the trench and constitute surface defects. The surface defects generate leakage current and the leakage current increases the off current of the TFT. As a result, it is impossible to avoid problems such as a decreasing contrast of FPD and a narrowed angle of view. In a method for reducing leakage current of the surface of the semiconductor substrate described in Japanese Patent Application, First Publication No. H04-349647, the surface state of a silicon semiconductor substrate is stabilized by bonding the uncombined bonds (dangling binds) with hydrogen through hydrogen plasma treatment of a surface of the trench using pure (100%) hydrogen gas under a flow rate of 10 to 1000 SCCM, hydrogen gas pressure of 10 to 500 Pa, RF current density of 0.005 to 0.5 W/cm2, and a treatment time of 1 to 60 minutes.
Japanese Patent Application, First Publication No. 2010-103324 describes a TFT in which the barrier film and the electrode film are bonded with high adhesion strength by the effect of a adhesion-enhancement film that is interposed between the barrier film made of a silicon oxide film and the pure copper film that constitute the drain electrode and the source electrode.
The adhesion-enhancement film is constituted of two regions composed of copper purification region formed on the side of the electrode, and a component concentrating region formed in the vicinity of interface with the barrier film. The component concentrating region is composed of Cu, Ca, oxygen, and Si, where peak concentration of Ca in the thickness direction is 5 to 20 atomic %, and peak concentration of oxygen in the thickness direction is 30 to 50 atomic %.
Japanese Patent No. 3302894 describes a preparation of an interconnect layer by forming a conductive layer, and subsequently heat treating the conductive layer in oxygen atmosphere, thereby forming a thermal oxide layer. In this method, the conductive layer is constituted of a material that is mainly composed of at least one first metal selected from the group consisting of Ag, Au, Cu, and Pt, and that includes at least one second metal selected from the group consisting of Ti, Zr, Hf, Ta, Nb, Si, B, La, Nd, Sm, Eu, Gd, Dy, Y, Yb, Ce, Mg, Th, and Cr. The thermal oxide layer formed on the surface of the conductive layer is constituted of a material that is mainly composed of the second metal such that the proportion of the second metal to the first metal is larger in the thermal oxide layer than in the conductive layer. The thus formed TFT has durability to treatments with various chemical substances and has an interconnect layer that is highly adhesive to the substrate.
It is known that durability of the gate interconnects and data interconnects formed on the array substrate are highly important as elements for determining the quality of the image of FPD. It is also known that signal delay of the input signal can be reduced, resulting in improvement of image quality, where the gate interconnects and the data interconnects have small durability. Because of its small durability, Cu has been used in gate interconnects or in data interconnects. However, use of Cu in the gate interconnects is accompanied with a problem of inferior contact properties of Cu with the substrate. As a solution for this problem, Japanese Patent Application First Publication, No. 2004-163901 describes use of Ti layer or Mo layer as a metal buffer layer interposed between the substrate and the Cu layer.
On the other hand, in accordance with remarkable increase of display size and integration of various FPDs in recent years, there is a demand for still higher adhesion strength between the stacked films constituting TFTs. However, in the conventional TFT described in Japanese Patent Application, First Publication, No. H04-349637, high adhesion strength that satisfies the above-described demand is not provided due to weak adhesion strength between the silicon oxide film (barrier film) and the pure copper film (electrode film) separated by the trench.
In the conventional type TFT described in Japanese Patent Application, First Publication No. 2010-103324, high adhesive strength is provided by the presence of adhesion enhancement film interposed between the silicon oxide film (barrier film) and the pure copper film (electrode film). However, it is necessary to modify the structure of apparatus due to the use of oxygen gas as the sputtering gas in the production process of TFTs, resulting in an increase of production costs and deterioration of productivity. Therefore, the technique of Japanese Patent Application, First Publication No. 2010-103324 included a severe problem in practical application to TFTs, since there is a demand for cost reduction of TFTs in accordance with the spread of large screen FPDs.
In some case of the recent production process of TFTs, the above-described hydrogen plasma treatment is performed after formation of the source electrode and the drain electrode. The conventional TFTs described in Japanese Patent No. 3302894 included problems of inferior hydrogen plasma durability such that the Cu alloy oxide layer is reduced by hydrogen plasma, resulting in deterioration of adhesion. On the other hand, where Cu was used as the first type metal, there was a problem of relatively high resistivity compared to the conventional Cu based material.
The post-process of the interconnect process described in, Japanese Patent Application, First Publication No. 2004-163901, where Cu is used as gate interconnects and Mo ad/or Ti are used as a metal buffer layer, often accompanies wet etching. However, it is difficult to etch Mo or Ti and Cu with the same etchant because of largely different electrochemical properties. Therefore, there was a problem in that etching must be performed using a plurality of etchant.
An object of the present invention is to provide a method that is capable of, using an existing sputtering apparatus, forming a Cu-alloy thin film interconnect that has high adhesion strength with a substrate, low resistivity, and excellent hydrogen plasma durability, and that can be etched with a single etchant. Another object of the present invention is to provide a Cu-alloy thin film interconnect that is formed by the production method and that has low resistivity and high hydrogen plasma durability.